/*
 * Copyright (C) 2024, Ingenic Semiconductor Co.,Ltd.
 * Author: Keven <keven.ywhan@ingenic.com>
 */

#ifndef __SOC_BASE_H__
#define __SOC_BASE_H__

#define DDRC_BASE         (0x134f0000)
#define DDR_MEM_PHY_BASE  (0x20000000)
#define MSC0_BASE         (0x13060000)
#define GPIO_BASE         (0x10010000)
#define SFC_BASE          (0x13440000)
#define UART0_BASE        (0x10030000)
#define CPM_BASE          (0x10000000)
#define CLINT_CTRL_BASE   (0x12a00000)
#define CCU_BASE          (0x12200000)

/* CCU RGE */
#define CCU_CSRR          (0x40)
#define CCU_MSCR          (0x60)
#define CCU_CFCR          (0xfe0)
#define CCU_PER           (0xf00)
#define CCU_CCR           (0x70)

#endif /* __SOC_BASE_H__ */

